A Survey on FPGA On-line Checking Methods

The purpose of FPGA on-line checking is to detect faults that occurs in-field. Depending on whether circuit logic is affected permanently, in-field faults can be categorized into temporal and permanent faults. Temporal faults may come from single-event-upset, ground bounce, power supply noise or crosstalk. Moreover, permanent faults are due to silicon aging, electro-migration and wire/device burn down. Permanent faults are the targeted fault-types for most on-line checking methods. Previous works on online fault detection are usually combined with the diagnostic steps. Researchers are interested in not only detect the fault but also know the potential fault locations. Depending on their fault diagnostic spatial resolution, the proposed methods can be categorized into fine-grained diagnostic approaches and coarse-grained diagnostic approaches. In fine-grained diagnostic approaches, faults locations are identified down to CLB level. This can be achieved by built-in self-test (BIST) [Abramovici04] [Shuthar06] or sequentially apply external test pattern on CLBs [Gericota03]. On the other hand, coarse-grained approaches identify fault locations to module-or column-level. Concurrent error detection (CED) codes are used in these approaches [Burress97][Mitra04]. Fine-grained resolution can be achieved using BIST. In [Abramovici99], each configurable logic block (CLB) is tested with built-in self-test by sequentially roving row-and column-under-test. This proposed method takes several seconds to test all resources but can achieve fine-grain resolution (within a CLB level) when a fault presents. A systematic method to locate a faulty CLB for this approach is latter presented in [Abramovici00] and [Abramovici04]. Moreover, interconnect resources fault detection and diagnosis is presented in [Stroud01]. In both CLB and interconnect diagnosis, divide-and-conquer approaches are used to gradually locate faults to a finer precision. In [Verma04], the diagnosabilities of the BIST method were proved. Particularly, one-diagnosable and two-diagnosable BIST units are analyzed. Furthermore, [Suthar05] proposed five test configurations to test the global interconnect resources within the BIST unit that yield significant test time reduction as apposed to [Stroud01]. M-BIST method, another noteworthy idea proposed in [Shuthar06], is to test both PLB and interconnect without fault-free assumptions on either of them. This method utilizes " iterative boostrapping " in which a fault-free CLB or interconnect was identified without previous knowledge on its faulty/fault-free status. Further testing is then based on these fault-free resources. In addition to BIST approach, JTAG can be used to perform online testing with the help of reconfiguration and read back. CLB-level resolution was reported using this method. [Gericota03] proposed two steps to test every resource …